The present invention relates to low power electrical circuits, and more particularly to low power short channel Metal-Oxide-Semiconductor (MOS) circuits.
Complementary Metal-Oxide-Semiconductor (CMOS) is a technology for constructing Integrated Circuits (ICs). CMOS technologies are used in microprocessors, microcontrollers, Static Random Access Memory (SRAM), Application Specific Integrated Circuits (ASIC), and wide varieties of electrical circuits. The word “complementary” refer to the fact that the typical design style with CMOS uses complementary pairs of p-channel and n-channel metal-oxide-semiconductor Field Effect Transistors (FETs). Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not waste as much power as other forms of logic, such as Transistor-Transistor Logic (TTL) or N-channel Metal-Oxide-Semiconductor (NMOS) logic, that normally have significant standby leakage current even when not changing state. By definition, “standby leakage current” is the current flowing through the power supply of a circuit when the circuit is not changing state. The standby leakage currents of CMOS circuits are typically much lower than that of other types of circuits. It was primarily for this reason that CMOS became the most used technology to be implemented in integrated circuits.
As IC technologies advanced, the channel lengths of MOS transistors have been reduced. Currently, transistors with channel length as short as 22 nanometers (nm) have been manufactured. The standby leakage currents of CMOS circuits increase rapidly with decreasing channel lengths of CMOS transistors. For CMOS circuits using transistors with channel lengths longer than 200 nm, the standby leakage currents of the CMOS circuits are typically negligible. On the other hand, short channel CMOS circuits can waste significant power even when the circuit is not changing state. Consequently, it is often necessary to provide power saving methods to reduce standby leakage currents for short channel CMOS circuits.
Currently, most of power saving methods are controlled by logic circuits called power management units. A prior art Power Management Unit (PMU) monitors the activities of circuit blocks, and turns off the power supply of a circuit block that is not in use in order to save power. FIG. 1(a) is a flowchart showing typical operations of a prior art PMU, and FIG. 2(a) is a timing diagram showing the power supply voltages of a circuit block controlled by a prior art PMU. At normal operation conditions, the substrate terminals and the source terminals of the p-channel transistor that are connected to the power source are connected to a power line at voltage Vdd, and the n-channel substrate terminals and the source terminals of n-channel transistors that are connected to power source are connected to a ground line at voltage Vss; the power supply voltage (Vpower) is equal to (Vdd−Vss) and it is typically set at a standard voltage (Vstd). Each generation of CMOS technology is optimized for a particular standard voltage. For examples, the standard voltage for 180 nm technology is typically 1.8 volts, Vstd is typically 1.2 volts for 130 nm technology, Vstd is typically 1.0 volt for 90 nm technologies, and so on. The prior art PMU monitors the activities of the whole circuit to determine whether a particular circuit block needs to work or not. If the circuit block needs to work, it stays in full power, which means that Vpower applied on the circuit block stays at Vstd. If a circuit block is no longer needed to work, the PMU can shut down the circuit block to save power. For example, the PMU found that starting from time T1 in FIG. 2(a), a circuit block is no longer needed. Typically, a prior art PMU cannot turn off the power immediately at time T1. When the power supply of a circuit block is turned off, the data stored in the volatile memory devices inside the circuit block can be lost. When the power is turned back on, the circuit may not return to previous state because the contents in memory devices can be different after power up. Examples of volatile memory devices include Static Random Access Memory (SRAM), Content Addressable Memory (CAM), registers, latches, flip-flops, and so on. It is typically necessary to store the contents of volatile memory devices before shutting down the power. As shown in FIG. 1(a), when the PMU determines to shut down a circuit block to save power, it typically needs to store data in memory devices into nonvolatile memory before turning off the power of the circuit block to save power. As shown in FIG. 2(a), the circuit block is not in use since time T1, but the PMU need to maintain in full power on the circuit block until time T3. The storage time (T3−T1) is used to store contents in memory devices into nonvolatile memory devices such as hard discs. This procedure can be time consuming, and it can burn a lot of power. After time T3, the PMU can shut down the power, and Vpower gradually approaches zero, as shown in FIG. 2(a). During this period of time, the PMU continues to monitor the activities of the whole circuit to determine whether the circuit in power saving mode is needed or not. If the circuit block is not needed, it can stay in power saving mode, as shown in FIG. 1(a). If the circuit block is needed, the PMU restarts the circuit block by turning on its power at time T2, as shown in FIG. 2(a). However, the circuit block is not ready to function until the data are restored back to the memory devices in the circuit block at time T4, as shown in FIG. 2(a). This recovery time (T4−T2) can be long, and the circuit block can consume a lot of power during recovery. After time T4, the circuit block is ready to restart normal operations, as illustrated in FIG. 2(a).
The operation of prior art PMUs can be very complex, especially when a circuit block comprises many memory devices. The procedures to shut down and restore a circuit block can be time consuming, and the processes can consume a lot of power. The PMU itself also can consume significant power. It is therefore highly desirable to develop power saving modes that support fast recovery time.
In U.S. Pat. No. 7,782,655 and in U.S. Pat. No. 8,164,969, Shau disclosed “Hybrid Subthreshold (SubVt) Circuits” that solved many problems of prior art power management units. FIG. 1(b) is a flowchart showing typical operations of a prior art Hybrid SubVt circuit. FIG. 2(b) is a timing diagram showing the voltages applied on a circuit block controlled by a prior art Hybrid SubVt controller, where NVps is the power connection to the source terminals of p-channel MOS transistors that are connected to power source, NVpb is the electrical connection to the substrate terminals of p-channel MOS transistors, NVns is the ground connection to the source terminals of n-channel MOS transistors that are connected to power source, and NVnb is the electrical connection to the substrate terminals of n-channel MOS transistors. At normal operation, Hybrid SubVt circuits operates in the same condition as typical CMOS circuits, where NVpb is connected to NVps at power supply voltage Vdd, NVnb is connected to NVns at ground voltage Vss, and the power supply voltage (Vpower) equals standard voltage (Vstd), as shown in the timing diagram in FIG. 2(b). A Hybrid SubVt controller monitors the activities of the whole circuit to determine whether a particular circuit block needs to work or not. If the circuit block needs to work, then it stays in full power, which means that Vpower of the circuit block stays at Vstd. If a circuit block is no longer needed to work, the circuit can be placed into subthreshold power saving mode, as shown in FIG. 1(b). At subthreshold power saving mode, the power supply voltage (Vpower) is reduced to a level that is lower than the threshold voltages (Vt) of the MOS transistors in the circuit block. Under SubVt mode, the standby leakage current of the circuit can be reduced by 99% or more relative to the standby leakage current of the same electrical circuit under normal operation mode, while all the memory devices still can hold their data. It is therefore possible to get into SubVt power saving mode immediately without the need to store the data in memory devices into nonvolatile memory devices. For example, the controller found that starting from time T1 in FIG. 2(a) the circuit block is no longer needed. Right after T1, the circuit can get into SubVt power saving mode, where NVpb is pulled up to a voltage Vpb that is higher than Vdd, NVnb is pulled down to a voltage Vns that is lower than Vss, the voltage on NVps is allowed to drop no lower than a voltage Vpt, and the voltage on Vns is allowed to rise no higher than a voltage Vnt, as shown in FIG. 2(b). The voltage difference (Vpt−Vnt) is controlled to be lower than Vt, so that the circuit block is under SubVt mode. During this period of time, the controller continues to monitor the activities of the whole circuit to determine whether the circuit in power saving mode is needed or not. If the circuit block is not needed, it can stay in SubVt mode, as shown in FIG. 1(b). If the circuit block is needed, the controller restarts the circuit block by going back to normal operation mode at time T2, as shown in FIG. 2(b). Since there is no need to restore data from nonvolatile memory devices, the circuit block can go back to normal operation mode instantly after time T2, as shown in FIG. 2(b).
Shau's hybrid SubVt circuits significantly reduced the wastes in power during storage time and recovery time. However, hybrid SubVt mode is applicable typically when the circuit block does not need to do any work. It is highly desirable to develop a power saving mode that is applicable on circuit blocks that need to do work.